1. Field of the Invention
The present invention relates, generally, to integrated circuit fabrication and, in preferred embodiments, to a bottom anti-reflective coating and hard mask for gate patterning and a method for forming the same.
2. Description of Related Art
The escalating requirements for high density and performance associated with ultra large scale integration require responsive changes in conductive patterns, which is considered one of the most demanding aspects of ultra large scale integration technology. High density demands for ultra large scale integration semiconductor wiring require increasingly denser arrays with minimal spacing between conductive lines. The increasing demands for high density impose correspondingly high demands on photolithographic techniques.
During the manufacture of a semiconductor device, light from a stepper is passed through a mask and the pattern transferred to the underlying photoresist layer. However, when the substrate underlying the photoresist layer is highly reflective, for example metal and polysilicon layers, light reflections can destroy the pattern resolution through several mechanisms, including off-normal incident light reflected back into photoresist that is intended to be masked, incident light reflected off device features that exposes xe2x80x9cnotchesxe2x80x9d in the photoresist, and thin film interference effects that lead to linewidth variations as a result of photoresist thickness changes are caused by irregular wafer topography.
Conventional photolithographic techniques employed during various phases in the manufacture of semiconductor devices involve the formation of an anti-reflective coating (ARC), also characterized as an anti-reflective layer (ARL), typically positioned between a semiconductor substrate and a photoresist material. Conventional ARCs are designed, by appropriate adjustment of variables such as composition, deposition conditions and reaction conditions, to exhibit the requisite optical parameters to suppress multiple interference effects caused by the interference of light rays propagating in the same direction due to multiple reflections in the photoresist film. The effective use of an ARC enables patterning and alignment without disturbance caused by such multiple interference, thereby improving line width accuracy and alignment.
It has been found that some line width variations are due to the inability of the ARC to reduce reflective layer reflectivity to a minimum. These reflectivity problems have been addressed by the use of bottom anti-reflective coatings (BARCs) underneath the resists.
In some applications, the BARC serves two functions during semiconductor memory manufacturing: (1) as a hard mask during self-aligned etch (SAE) and during self-aligned-source etch; and (2) as a bottom anti-reflective layer for photolithography at second gate masking.
Silicon oxynitride (SiON) by itself has been used as a BARC material. However, the thickness of SiON required to perform the function of a good hard mask is too thick to minimize reflectivity. For example, a typical thickness of a SiON BARC may be 100 nm. This thickness may result in non-uniform line width. The non-uniform line width is a result of lensing reflections of light into the photoresist from undulations in the topography of reflective layers under the BARC that are not completely phase cancelled by the BARC. Consequently, a second anti-reflective layer has been used in combination with a SiON layer to improve the performance of the BARC as both a hard mask and a bottom anti-reflective layer for photolithography.
FIG. 1 shows a double layer type BARC currently used in semiconductor device fabrication. Semiconductor device 100 has a substrate 102. A polysilicon layer 104 with a high reflectivity is formed on substrate 102. The polysilicon layer 104 is to be etched using the BARC as a hard mask. The BARC comprises an amorphous carbon layer 106 and a SiON layer 108. The amorphous carbon layer 106 is formed on top of the polysilicon layer 104. The SiON layer 108 is formed on top of the amorphous carbon layer 106. A photoresist pattern 110 is formed on top of the SiON layer 108 which defines, for example, a line pattern.
A double layer type BARC like that shown in FIG. 1 has the advantages of allowing the thickness of the anti-reflective layer to be appropriately adjusted to lower the reflectivity and, in addition, allowing the double layer type anti-reflective layer to function as a hard mask for use in an etching process.
However, there are also accompanying disadvantages of the double layer type anti-reflective layer structure shown in FIG. 1. One disadvantage of the semiconductor device 100 shown in FIG. 1 is that thin nitride layers such as SiON layer 108 are prone to pinhole defects that may affect the reliability of the semiconductor device. One common cause of pinhole defects in a SiON layer is outgassing during the chemical vapor deposition (CVD) process used to form the SiON layer. This outgassing creates localized non-uniformity of the plasma used in the CVD process which results in pinholes in the SiON layer. The pinholes may allow etchant to pass through the SiON layer and contact the amorphous carbon layer during photoresist etching. In addition, nitrogen dopant provided in the amorphous carbon to improve the etch selectivity of the amorphous carbon relative to polysilicon, may contaminate the photoresist. This may prevent the photoresist from being removed during the development process and may result in defects in the pattern formed on the polysilicon layer.
Another disadvantage of the semiconductor device 100 shown in FIG. 1 is that there exists a large compressive stress in the amorphous carbon layer 106 that results from large differences in coefficients of thermal expansion (CTE) between the amorphous carbon layer 106 and the polysilicon layer 104. Because the polysilicon layer 104 contracts to a different degree than the amorphous carbon layer 106 during the semiconductor device fabrication process, the amorphous carbon layer 106 experiences a permanent state of compressive stress. This stress may cause the patterned amorphous carbon to delaminate from the underlying polysilicon and take on a deformed pattern. When the patterned amorphous carbon is subsequently used as a hard mask to pattern the polysilicon layer 104, the deformed pattern will be transferred to the polysilicon layer 104.
These effects of the polysilicon layer etching process are undesirable, as they make it difficult to control the critical dimensions of the device features. Thus, the semiconductor device may be rejected during a final inspection step due to the deformed pattern on the polysilicon layer.
Embodiments of the invention pertain to a semiconductor device having a multi-layered anti-reflective coating and a method for fabricating the same. In accordance with a first preferred embodiment of the invention, a patternable layer is formed over a substrate. An anti-reflective coating is formed over the patternable layer. The anti-reflective coating includes an amorphous carbon layer formed over the patternable layer. The anti-reflective coating further includes a SiC layer formed over the amorphous carbon layer. A photoresist pattern is formed over the SiC layer. The SiC layer has a lower pinhole density than the pinhole density of silicon oxynitride. Thus, contamination of the photoresist by components of the amorphous carbon layer is reduced. Further, during the etching process, there is a reduction in undesired etching of the amorphous carbon layer due to etchant passing through a large number of pinhole defects in a silicon oxynitride layer.
In accordance with a second preferred embodiment of the invention, a polysilicon layer is formed over a substrate. The polysilicon layer is characterized by a first CTE. An anti-reflective coating is formed over the polysilicon layer. The anti-reflective coating includes a SiC layer formed over the polysilicon layer. The anti-reflective coating further includes a SiON layer formed over the SiC layer. A photoresist pattern is formed over the SiON layer. The SiC layer is characterized by a second CTE. The CTE of the SiC layer is closer to the CTE of the polysilicon layer than is a CTE of amorphous carbon. Thus, compressive stress is reduced in the SiC layer due to a closer match between the CTEs of the SiC layer and the polysilicon layer and, therefore, deformation of the SiC layer is reduced. This results in a reduction in the deformation of the pattern that will be transferred to the polysilicon layer.
In accordance with a third preferred embodiment of the invention, a polysilicon layer is formed over a substrate. The polysilicon layer is characterized by a first CTE. An anti-reflective coating is formed over the polysilicon layer. The anti-reflective coating includes a SiC buffer layer formed over the polysilicon layer. The anti-reflective coating further includes an amorphous carbon layer formed over the SiC buffer layer. The anti-reflective coating further includes a third layer formed over the amorphous carbon layer. A photoresist pattern is formed over the third layer. The SiC buffer layer is characterized by a second CTE. The second CTE is closer to the CTE of the polysilicon layer than is a CTE of amorphous carbon. Thus, compressive stress is reduced in the amorphous carbon layer due to the presence of the SiC buffer layer. Compressive stress is also reduced in the SiC buffer layer due to a closer match between the CTEs of the SiC buffer layer and the polysilicon layer and, therefore, deformation of the SiC buffer layer will be reduced. The third layer may be a SiON layer or an additional SiC layer. When the third layer is an additional SiC layer, it has the further advantages of a lower pinhole density, including reduced contamination of the photoresist pattern by components of the amorphous carbon layer and reduced etching of the amorphous carbon layer due to etchant passing through pinhole defects.